EVSR: Automatic Sizing Optimization of Digital Comparator based on Extended Variable Self-Built References

Abstract

The emergence of threshold-based digital comparators has revolutionized mixed-signal circuit systems, notably in high-speed ADCs. These comparators generate internal reference voltage autonomously, eliminating reliance on external sources. However, different voltages require varied internal logic gate sizes, impacting reference voltage accuracy, power, latency, and area. This divergence prevents direct application of conventional digital synthesis to these comparators. In this study, EVSR (Extended Variable Self-built References) is proposed for automatic sizing optimization. A non-linear programming model is introduced to minimize internal voltage error, solved by an efficient single comparator sizing (SCS) algorithm based on integer differential evolution and Nelder-Mead mechanisms. Additionally, for multi-bit flash ADCs, the comparator is refined for a more uniform distribution of internal voltage. The optimization of both error and energy-delay product through optimal SCS and dynamic programming (OPTSCS-DP) is accomplished by the multi-comparator sizing algorithm. Experimental results confirm the SCS-based digital comparator reaches a step threshold of 10mV. Compared to the best existing solution at the same 55nm process, the proposed design reduces power consumption by 72.25% and area by 41.18%. And our proposed OPTSCS-DP demonstrates a  enhancement in the Figure of Merit (FoM) compared to iterative SCS. (Code is available at https://github.com/ucas-xsw/DigitalCompapratorAlgorithm.)